PIC16F707 Datasheet, PDF (19/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
resets
Bank 0
00h^{( 2)}
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx xxxx xxxx
01h
02h^{( 2)}
03h^{( 2)}
04h^{( 2)}
TMR0
PCL
STATUS
FSR
Timer0 Module Register
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
Indirect Data Memory Address Pointer
0000 0000 0000 0000
0000 0000 0000 0000
C
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
05h
PORTA
PORTA Data Latch when written: PORTA pins when read
xxxx xxxx uuuu uuuu
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
09h
0Ah^{( 1),( 2)}
0Bh^{( 2)}
PORTE
PCLATH
INTCON
—
—
—
—
RE3
RE2
RE1
RE0 ---- xxxx ---- uuuu
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 0000 000u
0Ch
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF 0000 0000 0000 0000
0Dh
PIR2
TMR3GIF TMR3IF TMRBIF TMRAIF
—
—
—
CCP2IF 0000 ---0 0000 ---0
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON 0000 00-0 uuuu uu-u
11h
TMR2
Timer2 Module Register
0000 0000 0000 0000
12h
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3
SSPM2
SSPM1 SSPM0 0000 0000 0000 0000
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
—
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 0000 000x
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
—
—
DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh
ADRES
A/D Result Register
xxxx xxxx uuuu uuuu
1Fh
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON --00 0000 --00 0000
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 19