PIC16F707 Datasheet, PDF (170/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
19.2.5 RECEPTION
When the R/W bit of the received address byte is clear,
the master will write data to the slave. If an address
match occurs, the received address is loaded into the
SSPBUF register. An address byte overflow will occur
if that loaded address is not read from the SSPBUF
before the next complete byte is received.
An SSP interrupt is generated for each data transfer byte.
The BF, R/W and D/A bits of the SSPSTAT register are
used to determine the status of the last received byte.
FIGURE 19-10: I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
R/W = 0
Receiving Address
ACK
Receiving Data
ACK
Receiving Data
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL S ^{1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9}
P
SSPIF
BF
Cleared in software
SSPBUF register is read
Bus Master
sends Stop
condition
SSPOV
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
DS41418A-page 170
Preliminary
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