PIC16F707 Datasheet, PDF (184/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
21.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 21-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1⁽¹⁾
CLKOUT⁽²⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽³⁾
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
PC
Instruction
Fetched
Inst(PC) = Sleep
Instruction
Executed
Inst(PC - 1)
Processor in
Sleep
PC + 1
Inst(PC + 1)
Sleep
PC + 2
Interrupt Latency⁽⁴⁾
PC + 2
Inst(PC + 2)
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
Inst(0004h)
Dummy Cycle
0005h
Inst(0005h)
Inst(0004h)
Note 1:
2:
3:
4:
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON GIE
PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000
PIE1
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
PIE2
TMR3GIE TMR3IE TMRBIE TMRAIE —
—
—
CCP2IE 0000 ---0
PIR1
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
PIR2
TMR3GIF TMR3IF TMRBIF TMRAIF
—
—
—
CCP2IF 0000 ---0
STATUS IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
Value on all
other
Resets
0000 000x
0000 0000
0000 0000
0000 ---0
0000 0000
0000 ---0
000q quuu
DS41418A-page 184
Preliminary
 2010 Microchip Technology Inc.