PIC16F707 Datasheet, PDF (102/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
13.3 Timer1/3 Prescaler
Timer1 and Timer3 have four prescaler options allowing
1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits
of the TxCON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMRxH or TMRxL.
13.4 Timer1/3 Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator can
provide a clock source to Timer1 and/or Timer3. The
oscillator will continue to run during Sleep.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1/3.
13.5 Timer1/3 Operation in
Asynchronous Counter Mode
If control bit TxSYNC of the TxCON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected, then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 13.5.1 “Reading and Writing Timer1/3 in
Asynchronous Counter Mode”).
13.5.1
READING AND WRITING TIMER1/3
IN ASYNCHRONOUS COUNTER
MODE
Reading TMRxH or TMRxL while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMRxH:TMRxL register pair.
13.6 Timer1/3 Gate
Timer1/3 can be configured to count freely or the count
can be enabled and disabled using Timer1/3 gate
circuitry. This is also referred to as Timer1/3 gate count
enable.
Timer1/3 gate can also be driven by multiple selectable
sources.
13.6.1 TIMER1/3 GATE COUNT ENABLE
The Timer1/3 gate is enabled by setting the TMRxGE bit
of the TxGCON register. The polarity of the Timer1/3
gate is configured using the TxGPOL bit of the TxGCON
register.
When Timer1/3 gate (TxG) input is active, Timer1/3 will
increment on the rising edge of the Timer1/3 clock
source. When Timer1/3 gate input is inactive, no incre-
menting will occur and Timer1/3 will hold the current
count. See Figure 13-3 for timing details.
TABLE 13-4: TIMER1/3 GATE ENABLE
SELECTIONS
TxCLK TxGPOL TxG Timer1/3 Operation

0
0

0
1

1
0

1
1
Counts
Holds Count
Holds Count
Counts
13.6.2 TIMER1/3 GATE SOURCE
SELECTION
The Timer1/3 gate source can be selected from one of
four different sources. Source selection is controlled by
the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
DS41418A-page 102
Preliminary
 2010 Microchip Technology Inc.