RG82845SL5YQ Datasheet, PDF (87/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.6.13
SMLT1—Secondary Master Latency Timer Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
1Bh
00h
R/W
8 bits
This register controls the bus tenure of the MCH on AGP. MLT is an 8-bit register that controls
the amount of time the MCH, as an AGP/PCI bus master, can burst data on the AGP bus. The
count value is an 8-bit quantity; however, MLT[2:0] are reserved and have a value of 0 when
determining the count value. The MCH’s MLT is used to guarantee to the AGP master a minimum
amount of the system resources. When the MCH begins the first AGP FRAME# cycle after being
granted the bus, the counter is loaded and enabled to count from the assertion of FRAME#. If the
count expires while the MCH’s grant is removed (due to AGP master request), the MCH will lose
the use of the bus, and the AGP master agent may be granted the bus. If the MCH’s bus grant is
not removed, the MCH continues to own the AGP bus, regardless of the MLT expiration or idle
condition. Note that the MCH always properly terminates an AGP transaction, with FRAME#
negation prior to the final data transfer.
The number of clocks programmed in the MLT represents the guaranteed time slice (measured in
66 MHz AGP clocks) allotted to the MCH, after which it must complete the current data transfer
phase and then surrender the bus as soon as its bus grant is removed. For example, if the MLT is
programmed to 18h, the value is 24 AGP clocks. The default value of MLT is 00h and disables
this function. When the MLT is disabled, the burst time for the MCH is unlimited (i.e., the MCH
can burst forever).
Bit
Description
7:3
Secondary MLT Counter Value. Default=0s (i.e., SMLT disabled)
2:0
Reserved.
Intel^® 82845 MCH for SDR Datasheet
87