RG82845SL5YQ Datasheet, PDF (106/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

System Address Map
R
4.5.2
AGP Interface Decode Rules
Cycles Initiated Using AGP FRAME# Protocol
The MCH does not support any AGP FRAME# access targeting the hub interface. The MCH
claims AGP-initiated memory read and write transactions decoded to the system memory range or
the Graphics Aperture range. All other memory read and write requests will be master-aborted by
the AGP initiator as a consequence of MCH not responding to a transaction.
Under certain conditions, the MCH restricts access to the DOS Compatibility ranges governed by
the PAM registers by distinguishing access type and destination bus. The MCH does NOT accept
AGP FRAME# write transactions to the compatibility ranges if the PAM designates system
memory as writeable. If accesses to a range are not write-enabled by the PAM, the MCH does not
respond and the cycle results in a master-abort. The MCH accepts AGP FRAME# read
transactions to the compatibility ranges if the PAM designates system memory as readable. If
accesses to a range are not read-enabled by the PAM, the MCH does not respond and the cycle
results in a master-abort.
If agent on AGP issues an I/O, PCI Configuration or PCI Special Cycle transaction, the MCH does
not respond and cycle results in a master-abort.
Cycles Initiated Using AGP PIPE# or SB Protocol
All cycles must reference system memory; that is, system memory address range (including PAM)
or Graphics Aperture range (also physically mapped within system memory but using different
address range). AGP accesses to SMM space are not allowed. AGP-initiated cycles that target
system memory are not snooped on the host bus, even if they fall outside of the AGP aperture
range.
If a cycle is outside of the system memory range, then it terminates as follows:
• Reads remap to memory address 0h, return data from address 0h, and set the IAAF error bit in
ERRSTS register in device 0
• Writes are terminated internally without affecting any chip signals or system memory
AGP Accesses to MCH that Cross Device Boundaries
For AGP FRAME# accesses, when an AGP master gets disconnected, it resumes at the new
address which allows the cycle to be routed to or claimed by the new target. Therefore, the target
on potential device boundaries should disconnect accesses. The MCH disconnects AGP FRAME#
transactions on 4 KB boundaries.
AGP PIPE# and SBA accesses are limited to 256 bytes and must hit system memory. Read
accesses crossing a device boundary will return invalid data when the access crosses out of system
memory. Write accesses crossing out of system memory will be discarded. The IAAF Error bit will
be set.
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Intel^® 82845 MCH for SDR Datasheet