RG82845SL5YQ Datasheet, PDF (14/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Introduction
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Intel^® 845 Chipset System Architecture
The MCH provides the processor interface, system memory interface, AGP interface, and hub
interface in an 845 chipset desktop platform. The processor interface supports the Pentium 4
processor subset of the Extended Mode of the Scalable Bus Protocol. The MCH supports a single
channel of PC133 SDRAM. The MCH contains advanced power management logic. The 845
chipset platform supports the I/O Controller Hub 2 (ICH2) to provide the features required by a
desktop platform.
Intel^® 82801BA I/O Controller Hub 2 (ICH2)
The ICH2 is a highly integrated multifunctional I/O Controller Hub that provides the interface to
the PCI Bus and integrates many of the functions needed in today’s PC platforms. The MCH and
ICH2 communicate over a dedicated hub interface. The 82801BA ICH2 Functions and capabilities
include:
• PCI Rev 2.2 compliant with support for 33 MHz PCI operations
• Supports up to 6 Request/Grant pairs (PCI slots)
• Power management logic support
• Enhanced DMA controller, interrupt controller, and timer functions
• Integrated IDE controller; Ultra ATA/100/66/33
• USB host interface; 2 host controllers and supports 4 USB ports
• Integrated LAN controller
• System Management Bus (SMBus) compatible with most I²C devices; ICH2 has both bus
master and slave capability
• AC ’97 2.1 compliant link for audio and telephony codecs; up to 6 channels (ICH2)
• Low Pin Count (LPC) interface
• FWH Interface (FWH Flash BIOS support)
• Alert on LAN* (AOL and AOL2)
Intel^® 82845 MCH Overview
The MCH role in a system is to manage the flow of information between its four interfaces: the
system bus, the memory interface, the AGP port, and the hub interface. The MCH arbitrates
between the four interfaces, when each initiates an operation. While doing so, the MCH supports
data coherency via snooping and performs address translation for access to AGP Aperture
memory. To increase system performance, the MCH incorporates several queues and a write
cache.
The MCH is in a 593 pin FC-BGA package and contains the following functionality:
• Supports single Pentium 4 processor configuration at 400 MHz
• AGTL+ system bus with integrated termination supporting 32-bit system bus addressing
• Up to 3 GB (w/ 512 Mb technology) of PC133 SDRAM
• 1.5 V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability
• 8 bit, 66 MHz 4x hub interface to the ICH2
• Distributed arbitration for highly concurrent operation
Intel^® 82845 MCH for SDR Datasheet