RG82845SL5YQ Datasheet, PDF (117/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Functional Description
R
5.4
5.4.1
MCH Retry/Disconnect Conditions
The MCH generates retry/disconnect according to the AGP Interface Specification, Revision 2.0
rules when being accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP FRAME#-to-system memory read cycle is retried by the MCH, it is processed
internally as a delayed transaction. The MCH supports the delayed transaction mechanism on the
AGP target interface for the transactions issued using AGP FRAME# protocol. This mechanism is
compatible with the PCI Local Bus Specification, Revision 2.1. The process of latching all
information required to complete the transaction, terminating with Retry, and completing the
request without holding the master in wait-states is called a delayed transaction.
The MCH latches the address and command when establishing a delayed transaction. The MCH
generates a delayed transaction on the AGP only for AGP FRAME# to system memory read
accesses. The MCH does not allow more than one delayed transaction access from AGP at any
time.
Power and Thermal Management
An 845 chipset platform is compliant with the following specifications:
• APM, Revision 1.2
• ACPI, Revision 1.0b
• PCI Power Management, Revision 1.0
• PC ’99, Revision 1.0
• PC ’99A
• PC ’01, Revision 1.0
Processor Power State Control
• C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is
deasserted, and the processor core is active. The processor can service snoops and maintain cache
coherency in this state.
• Stop-Grant State: This function can be enabled or disabled via a configuration bit. When this function
is enabled, STPCLK# is asserted to place the processor into the C2 state with a programmable
duty cycle. This is an ACPI defined function but BIOS or APM (via BIOS) can use this
facility.
Intel^® 82845 MCH for SDR Datasheet
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