RG82845SL5YQ Datasheet, PDF (51/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.5.11
SVID—Subsystem Vendor Identification (Device 0)
Offset:
Default:
Access:
Size:
2C–2Dh
0000h
R/WO
16 bits
This value is used to identify the vendor of the subsystem.
Bit
Description
15:0 Subsystem Vendor ID. (Default = 0000h). This field should be programmed during boot-up.
After this field is written once, it becomes read only.
3.5.12
SID—Subsystem Identification (Device 0)
Offset:
Default:
Access:
Size:
2E–2Fh
0000h
R/WO
16 bits
This value is used to identify a particular subsystem.
Bit
Description
15:0 Subsystem ID. (Default = 0000h). This field should be programmed during boot-up. After this
field is written once, it becomes read only.
3.5.13
CAPPTR—Capabilities Pointer (Device 0)
Offset:
Default:
Access:
Size:
34h
E4h
RO
8 bits
The CAPPTR provides the offset that is the pointer to the location where the AGP standard
registers are located.
Bit
Description
7:0
AGP Standard Register Block Pointer Address. This address pointer indicates to software
where it can find the beginning of the AGP register block.
E4h = AGP register block beginning address.
Intel^® 82845 MCH for SDR Datasheet
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