RG82845SL5YQ Datasheet, PDF (25/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Signal Description
R
2.4.2
AGP Flow Control Signals
Signal Name
Type
Description
RBF#
WBF#
I
AGP
I
AGP
Read Buffer Full: RBF# indicates if the master is ready to accept
previously requested low priority read data. When RBF# is asserted, the
MCH is not allowed to initiate the return low priority read data. That is, the
MCH can finish returning the data for the request currently being
serviced. RBF# is only sampled at the beginning of a cycle. If the AGP
master is always ready to accept return read data, then it is not required
to implement this signal.
During FRAME# Operation: Not Used.
Write-Buffer Full: Indicates if the master is ready to accept fast write
data from the MCH. When WBF# is asserted, the MCH is not allowed to
drive fast write data to the AGP master. WBF# is only sampled at the
beginning of a cycle. If the AGP master is always ready to accept fast
write data, then it is not required to implement this signal.
During FRAME# Operation: Not Used.
2.4.3
AGP Status Signals
Signal Name
Type
Description
ST[2:0]
O
AGP
Status: ST[2:0] provides information from the arbiter to an AGP Master
on what it may do. ST[2:0] only have meaning to the master when its
G_GNT# is asserted. When G_GNT# is deasserted, these signals have
no meaning and must be ignored. Refer to the AGP Interface
Specification, Revision 2.0 for further explanation of the ST[2:0] values
and their meanings.
During FRAME# Operation: These signals are not used during
FRAME#-based operation, except that a ‘111’ indicates that the master
may begin a FRAME# transaction.
Intel^® 82845 MCH for SDR Datasheet
25