RG82845SL5YQ Datasheet, PDF (120/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Electrical Characteristics
R
6.3
Signal Groups
The signal description includes the type of buffer used for the particular signal:
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The MCH integrates most AGTL+ termination resistors.
AGP
AGP interface signals. These signals are compatible with AGP 2.0 1.5 V
Signaling Environment DC and AC Specifications. The buffers are not 3.3 V
tolerant.
HI CMOS Hub Interface 1.8 V CMOS buffers.
SM CMOS System memory 3.3 V CMOS buffers.
Table 20. Signal Groups
Signal
Group
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
(k)
(l)
(m)
(n)
(o)
(p)
(r)
Signal Type
AGTL+ I/O
AGTL+ Output
AGTL+ Input
Host Reference
Voltages
AGP I/O
AGP Input
AGP Output
AGP Reference
Voltage
Hub Interface’s
CMOS I/O
Hub Interface
Reference Voltage
SDRAM CMOS I/O
SDRAM CMOS
Output
SDRAM CMOS Input
SDRAM Reference
Voltage
CMOS Input
CMOS Input
AGTL+ Termination
Voltage
Signals
ADS#, BNR#, BR0#,DBSY#, DBI[3:0]#, DRDY#, HA[31:3]#,
HADSTB[1:0] #, HD[63:0]#, HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#,
HITM#, HREQ[4:0]#
BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]#
HLOCK#
HVREF, HSWING[1:0]
AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, G_FRAME#,
G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0],
G_C/BE[3:0]#, G_PAR
PIPE#, SBA[7:0], RBF#, WBF#, SB_STB, SB_STB#, G_REQ#
ST[2:0], G_GNT#
AGPREF
HI_[10:0], HI_STB, HI_STB#
HI_REF
SDQ[63:0], SCB[7:0]
SCS[11:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#,
SCKE[5:0], SCK[11:0], RDCLKO
RDCLKI
SDREF
TESTIN#
RSTIN# (3.3V)
VTT
120
Intel^® 82845 MCH for SDR Datasheet