RG82845SL5YQ Datasheet, PDF (85/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.6.8
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
R/W
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as
a read/write to prevent standard PCI-PCI bridge configuration software from getting “confused”.
Bit
Description
7:3
Not applicable but supports read/write operations. (Reads return previously written data.)
2:0
Reserved.
3.6.9
HDR1—Header Type Register (Device 1)
Offset:
Default:
Access:
Size:
0Eh
01h
RO
8 bits
This register identifies the header layout of the configuration space.
Bit
Descriptions
7:0
This read only field always returns 01h when read. Writes have no effect.
3.6.10
PBUSN1—Primary Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
18h
00h
RO
8 bits
This register identifies that “virtual” PCI-PCI Bridge is connected to bus #0.
Bit
7:0
Bus Number. Hardwired to 0.
Descriptions
Intel^® 82845 MCH for SDR Datasheet
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