RG82845SL5YQ Datasheet, PDF (102/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

System Address Map
R
4.1.8
4.1.9
4.1.10
AGP Aperture Space (Device 0 BAR)
Processors and AGP devices communicate through a special buffer called the “graphics aperture”
(APBASE to APBASE + APSIZE). This aperture acts as a window into main system memory and
is defined by the APBASE and APSIZE configuration registers of the MCH. Note that the AGP
aperture must be above the top of memory and must not intersect with any other address space.
AGP Memory and Prefetchable Memory
Plug-and-play software configures the AGP memory window to provide enough memory space for
the devices behind this PCI-to-PCI bridge. Accesses whose addresses fall within this window are
decoded and forwarded to AGP for completion. The address ranges are:
• M1
MBASE1 to MLIMIT1
• PM1
PMBASE1 to PMLIMIT1
Note that these registers must be programmed with values that place the AGP memory space
window between the value in the TOM register and 4 GB. In addition, neither region should
overlap with any other fixed or relocatable area of memory.
Hub Interface Subtractive Decode
All accesses that fall between the value programmed into the TOM register and 4 GB
(i.e., TOM to 4 GB) are subtractively decoded and forwarded to the hub interface if they do not
decode to a space that corresponds to another device.
4.2
AGP Memory Address Ranges
The MCH can be programmed to direct memory accesses to the AGP bus interface when
addresses are within either of two ranges specified via registers in MCH device 1 configuration
space. The first range is controlled via the Memory Base Address (MBASE1) register and
Memory Limit Address (MLIMIT1) register. The second range is controlled via the Prefetchable
Memory Base Address (PMBASE1) register and Prefetchable Memory Limit Address
(PMLIMIT1) register
The MCH positively decodes memory accesses to AGP memory address space as defined by the
following equations:
• Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
• Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
The plug-and-play configuration software programs the effective size of the range and it depends
on the size of memory claimed by the AGP device.
Note: The MCH device 1 memory range registers described above are used to allocate memory address
space for any devices sitting on AGP bus that require such a window.
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Intel^® 82845 MCH for SDR Datasheet