RG82845SL5YQ Datasheet, PDF (77/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
Bit
Description
4
SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR).
0 = Disable.
1 = Enable. Generation of the hub interface SERR message is enabled when an AGP access
occurs to an address outside of the graphics aperture.
3
SERR on Invalid AGP Access (IAAF_SERR).
0 = Disable.
1 = Generation of the hub interface SERR message is enabled when an AGP access occurs to
an address outside of the graphics aperture and either to the 640 KB – 1 MB range or above
the top of memory.
2
SERR on Invalid Translation Table Entry (ITTEF_SERR).
0 = Disable.
1 = Enable. Generation of the hub interface SERR message is enabled when an invalid
translation table entry was returned in response to an AGP access to the graphics aperture.
1
SERR Multiple-Bit DRAM ECC Error (DMERR_SERR).
0 = Disable. For systems not supporting ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system
memory controller detects a multiple-bit error.
0
SERR on Single-bit ECC Error (DSERR).
0 = Disable. For systems that do not support ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system
memory controller detects a single bit error.
Intel^® 82845 MCH for SDR Datasheet
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