RG82845SL5YQ Datasheet, PDF (108/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Functional Description
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5.1.2
5.1.3
System Bus Interrupt Delivery
The Pentium 4 processor supports the system bus interrupt delivery; the APIC serial bus interrupt
delivery mechanism is not supported. Interrupt-related messages are encoded on the system bus as
“Interrupt Message Transactions”. In an 845 chipset platform, system bus interrupts can originate
from the processor on the system bus, or from a downstream device on the hub interface or AGP.
In the later case the MCH drives the “Interrupt Message Transaction” onto the system bus.
In an 845 chipset platform, the ICH2 contains IOxAPICs, and its interrupts are generated as
upstream hub interface memory writes. Furthermore, PCI 2.2 defines MSIs (Message Signaled
Interrupts) that are also in the form of memory writes. A PCI 2.2 device can generate an interrupt
as an MSI cycle on it’s PCI bus, instead of asserting a hardware signal to the IOxAPIC. The MSI
can be directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface
memory write. Alternatively, the MSI can be directed directly to the system bus. The target of a
MSI is dependent on the address of the interrupt memory write. The MCH forwards inbound hub
interface and AGP (PCI semantic only) memory writes to address 0FEEx_xxxxh, to the system bus
as “Interrupt Message Transactions”.
Upstream Interrupt Messages
The MCH accepts message-based interrupts from AGP (PCI semantics only) or its hub interface
and forwards them to the system bus as Interrupt Message Transactions. The interrupt messages
presented to the MCH are in the form of memory writes to address 0FEEx_xxxxh. At the hub
interface or AGP interface, the memory write interrupt message is treated like any other memory
write; it is either posted to the inbound data buffer (if space is available) or retried (if data buffer
space is not immediately available). Once posted, the memory write from AGP or the hub interface
to address 0FEEx_xxxxh is decoded as a cycle that needs to be propagated by the MCH to the
system bus as an Interrupt Message Transaction.
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Intel^® 82845 MCH for SDR Datasheet