RG82845SL5YQ Datasheet, PDF (26/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Signal Description
R
2.4.4
2.4.5
AGP Strobes Signals
Signal Name
Type
Description
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
SB_STB
SB_STB#
I/O
(s/t/s)
AGP
I/O
(s/t/s)
AGP
I/O
(s/t/s)
AGP
I/O
(s/t/s)
AGP
I
AGP
I
AGP
Address/Data Bus Strobe-0: This signal provides timing for 2x and 4x
data on AD[15:0] and the C/BE[1:0]# signals. The agent that is providing
the data drives this signal.
Address/Data Bus Strobe-0 Compliment: Differential strobe pair that
provides timing information for the AD[15:0] and C/BE[1:0]# signals. The
agent that is providing the data drives this signal.
Address/Data Bus Strobe-1: This signal provides timing for 2x- and 4x-
clocked data on AD[31:16] and C/BE[3:2]# signals. The agent that is
providing the data drives this signal.
Address/Data Bus Strobe-1 Compliment: The differential compliment
to the AD_STB1 signal. It is used to provide timing for 4x-clocked data.
Sideband Strobe: This signal provides timing for 2x- and 4x- clocked
data on the SBA[7:0] bus. It is driven by the AGP master after the system
has been configured for 2x- or 4x- clocked sideband address delivery.
Sideband Strobe Compliment: SB_STB# is the differential compliment
to the SB_STB signal. It is used to provide timing for 4x-clocked data.
AGP/PCI Signals
For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate
similar to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals
are defined below.
Signal Name
G_FRAME#
G_IRDY#
G_TRDY#
G_STOP#
Type
I/O
s/t/s
AGP
I/O
s/t/s
AGP
I/O
s/t/s
AGP
I/O
s/t/s
AGP
Description
FRAME: During FRAME# Operations, G_FRAME# is an output when the
MCH acts as an initiator on the AGP Interface.
Initiator Ready#: This signal indicates the AGP compliant master is
ready to provide all write data for the current transaction. Once G_IRDY#
is asserted for a write operation, the master is not allowed to insert wait
states. The master is never allowed to insert a wait state during the initial
data transfer (32 bytes) of a write transaction. However, it may insert wait
states after each 32-byte block is transferred.
Target Ready: This signal indicates the AGP compliant target is ready to
provide read data for the entire transaction (when the transfer size is less
than or equal to 32 bytes) or is ready to transfer the initial or subsequent
block (32 bytes) of data when the transfer size is greater than 32 bytes.
The target is allowed to insert wait states after each block (32 bytes) is
transferred on write transactions.
STOP: G_STOP Is an input when the MCH acts as a FRAME#-based
AGP initiator and an output when the MCH acts as a FRAME#-based
AGP target. G_STOP# is used for disconnect, retry, and abort
sequences on the AGP interface.
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Intel^® 82845 MCH for SDR Datasheet