RG82845SL5YQ Datasheet, PDF (20/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Signal Description
Figure 1. Intel^® MCH Simplified Block Diagram
HA[31:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
CPURST#
BR0#
DBI[3:0]#
HADSTB[1:0]#
HDSTBP[3:0]/HDSTBN[3:0]
SCS[11:0]#
S M A [12:0]
SBS[1:0]
SRAS#
SCAS#
SWE#
SDQ[63:0]
SCB[7:0]
SCKE[5:0]
RDCLKO
RDCLKIN
HI_[10:0]
HI_STB, HI_STB#
P ro c es s or
System
Bus
Interface
System
M e m o ry
SDRAM
Interface
Hub
Interface
AGP
Interface
Voltage
Refernce,
PLL Power
Clocks
and
Reset
R
SBA[7:0]
PIPE#
ST[2:0]
RBF#
WBF#
AD_STB[1:0], AD_STB[1:0]#
SBSTB, SBSTB#
AGPRCOMP
G_FRAME#
G_IRDY#
G_TRDY#
G_STOP#
G_DEVSEL#
G_REQ#
G_GNT#
G_AD[31:0]
G_C/BE[3:0]#
G_PAR
HVREF
SDREF
HI_REF
AGPREF
HLRCOMP
GRCOMP
HR C O M P [1:0]
HS W N G [1:0]
SMRCOMP
VCC1_5
VCC1_8
VCCSM
VCCA[1:0]
VTT
VSS
VSSA[1:0]
BCLK, BCLK#
66IN
SCK[11:0]
RSTIN#
TESTIN#
block_dia_845
20
Intel^® 82845 MCH for SDR Datasheet