RG82845SL5YQ Datasheet, PDF (32/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
Term
Reserved
Registers
Default Value
upon a Reset
Description
In addition to reserved bits within a register, the MCH contains address locations in the
configuration space that are marked “Reserved”. When a “Reserved” register location
is read, a random value is returned. (“Reserved” registers can be 8-, 16-, or 32-bit in
size). Registers that are marked as “Reserved” must not be modified by system
software. Writes to “Reserved” registers may cause system failure.
Upon a Full Reset, the MCH sets all of its internal configuration registers to
predetermined default states. Some register values at reset are determined by
external strapping options. The default state represents the minimum functionality
feature set required to successfully bring up the system. Hence, it does not represent
the optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, operating
parameters and optional system features that are applicable, and to program the MCH
registers accordingly.
3.2
PCI Bus Configuration Space Access
The MCH and ICH2 are physically connected by the hub interface. From a configuration
standpoint, the hub interface is PCI bus 0. As a result, all devices internal to the MCH and ICH2
appear to be on PCI bus 0. The system’s primary PCI expansion bus is physically attached to the
ICH2 and, from a configuration perspective appears to be a hierarchical PCI bus behind a PCI-to-
PCI bridge and, therefore, has a programmable PCI Bus number. Note that the primary PCI bus
is referred to as PCI_A in this document and is not PCI bus #0 from a configuration
standpoint. The AGP appears to system software to be a real PCI bus behind PCI-to-PCI bridges
resident as devices on PCI bus 0.
The MCH contains two PCI devices within a single physical component. The configuration
registers for the four devices are mapped as devices residing on PCI bus 0.
• Device 0: Host-Hub Interface Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus 0. Physically Device 0 contains the standard PCI registers, DRAM registers, the
Graphics Aperture controller, and other MCH specific registers.
• Device 1: Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing
on PCI bus 0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the
standard AGP/PCI configuration registers (including the AGP I/O and memory address
mapping).
Table 6 shows the Device # assignment for the various internal MCH devices.
Table 6. Intel^® MCH Internal Device Assignments
MCH Function
Bus 0, Device #
DRAM Controller/8 bit HI_A Controller
Host-to-AGP Bridge (virtual P2P)
Device 0
Device 1
NOTE: A physical PCI bus 0 does not exist. The hub interface and the internal devices in
the MCH and ICH2, logically constitute PCI Bus 0 to configuration software.
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Intel^® 82845 MCH for SDR Datasheet