RG82845SL5YQ Datasheet, PDF (31/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3
3.1
Register Description
The MCH contains two sets of software accessible registers, accessed via the host processor I/O
address space:
• Control registers I/O mapped into the processor I/O space, which control access to PCI and
AGP configuration space (see Section 3.3).
• Internal configuration registers residing within the MCH are partitioned into two logical
device register sets (“logical” since they reside within a single physical device). The first
register set is dedicated to Host-HI Bridge functionality (i.e., DRAM configuration, other
chip-set operating parameters and optional features). The second register block is dedicated to
Host-AGP Bridge functions (controls AGP interface configurations and operating
parameters).
The MCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification.
The MCH internal registers (I/O Mapped and configuration registers) are accessible by the
processor. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities,
with the exception of CONF_ADDR which can only be accessed as a DWord. All multi-byte
numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts
of the field).
Register Terminology
Term
Description
RO
R/W
R/W/L
R/WC
R/WO
L
Reserved Bits
Read Only. If a register is read only, writes to this register have no effect.
Read/Write. A register with this attribute can be read and written.
Read/Write/Lock. A register with this attribute can be read, written, and Locked.
Read/Write Clear. A register bit with this attribute can be read and written. However, a
write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Read/Write Once. A register bit with this attribute can be written to only once after
power up. After the first write, the bit becomes read only.
Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
Some of the MCH registers described in this section contain reserved bits. These bits
are labeled “Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note that software does not need to perform a read-merge-write
operation for the Configuration Address (CONF_ADDR) register.
Intel^® 82845 MCH for SDR Datasheet
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