RG82845SL5YQ Datasheet, PDF (86/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.6.11
SBUSN1—Secondary Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
19h
00h
R/W
8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI
bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to AGP.
Bit
Descriptions
7:0
Bus Number. Programmable. Default = 00h.
3.6.12
SUBUSN1—Subordinate Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
1Ah
00h
R/W
8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to AGP.
Bit
Descriptions
7:0
Bus Number. Programmable. Default = 0.
86
Intel^® 82845 MCH for SDR Datasheet