RG82845SL5YQ Datasheet, PDF (101/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

System Address Map
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4.1.4 TSEG SMM Memory Space
The TSEG SMM space (TOM – TSEG to TOM) allows system management software to partition
a region of system memory just below the top of low memory (TOM) that is accessible only by
system management software. This region may be 128 KB, 256 KB, 512 KB, or 1 MB in size,
depending on the ESMRAMC.TSEG_SZ field. SMM memory is globally enabled by
SMRAM.G_SMRAME. Requests can access SMM system memory when either SMM space is
open (SMRAM.D_OPEN) or the MCH receives an SMM code request on its system bus. To
access the TSEG SMM space, TSEG must be enabled by ESMRAMC.T_EN. When all of these
conditions are met, then a system bus access to the TSEG space (between TOM–TSEG and TOM)
is sent to system memory. If the high SMRAM is not enabled or if the TSEG is not enabled, then
all memory requests from all interfaces are forwarded to system memory. If the TSEG SMM space
is enabled, and an agent attempts a non-SMM access to TSEG space, then the transaction is
specially terminated.
Note: Hub interface and AGP originated accesses are not allowed to SMM space.
4.1.5
IOAPIC Memory Space
The IOAPIC space (0_FEC0_0000h to 0_FEC7_FFFFh) is used to communicate with IOAPIC
interrupt controllers that may be populated on the hub interface. Since it is difficult to relocate an
interrupt controller using plug-and-play software, fixed address decode regions have been
allocated for them. Processor accesses to the IOAPIC0 region are always sent to the hub interface.
4.1.6
System Bus Interrupt APIC Memory Space
The system bus interrupt space (0_FEE0_0000h to 0_FEEF_FFFFh) is the address used to deliver
interrupts to the system bus. Any device on AGP may issue a memory write to 0FEEx_xxxxh. The
MCH forwards this memory write, along with the data, to the system bus as an Interrupt Message
Transaction. The MCH terminates the system bus transaction by providing the response and
asserting TRDY#. This memory write cycle does not go to system memory.
4.1.7
High SMM Memory Space
The HIGHSMM space (0_FEDA_0000h to 0_FEDB_FFFFh) allows cacheable access to the
compatible SMM space by re-mapping valid SMM accesses between 0_FEDA_0000 and
0_FEDB_FFFF to accesses between 0_000A_0000 and 0_000B_FFFF. The accesses are
remapped when SMRAM space is enabled; an appropriate access is detected on the system bus,
and when ESMRAMC.H_SMRAME allows access to high SMRAM space. SMM memory
accesses from any hub interface or AGP are specially terminated: reads are provided with the
value from address 0 while writes are ignored entirely.
Intel^® 82845 MCH for SDR Datasheet
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