RG82845SL5YQ Datasheet, PDF (18/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Introduction
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1.4.7
1.4.8
System Interrupts
The MCH supports both Intel 8259 and Pentium 4 processor interrupt delivery mechanisms. The
serial APIC interrupt mechanism is not supported.
Intel 8259 support consists of flushing inbound hub interface write buffers when an Interrupt
Acknowledge cycle is forwarded from the system bus to the hub interface.
The MCH supports the Pentium 4 processor interrupt delivery mechanism. IOxAPIC and PCI MSI
interrupts are generated as memory writes. The MCH decodes upstream memory writes to the
range 0FEE0_0000h–0FEEF_FFFFh from AGP and the hub interface as message-based interrupts.
The MCH forwards the memory writes, along with the associated write data, to the system bus as
an interrupt message transaction. Note that since this address does not decode as part of system
memory, the write cycle and the write data are not forwarded to system memory via the write
buffer. The MCH provides the response and TRDY# for all interrupt message cycles, including the
ones originating from the MCH. The MCH supports interrupt re-direction for inter-processor
interrupts (IPIs) as well as upstream interrupt memory writes.
For message-based interrupts, system write-buffer coherency is maintained by relying on strict
ordering of memory writes. The MCH ensures that all memory writes received from a given
interface prior to an interrupt message memory write are delivered to the system bus for snooping
in the same order that they occur on the given interface.
Powerdown Flow
Since the MCH is powered down during STR, the MCH cannot maintain any state information
when exiting STR. Thus, the entire initialization process when exiting STR must be performed by
the BIOS via accesses to the DRC2 register.
Entry into STR (ACPI S3) is initiated by the Operating System (OS), based on detecting a lack of
system activity. The OS unloads all system device drivers as part of the process of entering STR.
The OS then writes to the PM1_CNT I/O register in the ICH2 to trigger the transition into STR.
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Intel^® 82845 MCH for SDR Datasheet