RG82845SL5YQ Datasheet, PDF (4/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

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3.5 Host-Hub Interface Bridge Device Registers (Device 0)......................................43
3.5.1 VID—Vendor Identification Register (Device 0) ....................................45
3.5.2 DID—Device Identification Register (Device 0).....................................45
3.5.3 PCICMD—PCI Command Register (Device 0) .....................................46
3.5.4 PCISTS—PCI Status Register (Device 0).............................................47
3.5.5 RID—Revision Identification Register (Device 0)..................................48
3.5.6 SUBC—Sub-Class Code Register (Device 0).......................................48
3.5.7 BCC—Base Class Code Register (Device 0)........................................48
3.5.8 MLT—Master Latency Timer Register (Device 0) .................................49
3.5.9 HDR—Header Type Register (Device 0) ..............................................49
3.5.10 APBASE—Aperture Base Configuration Register (Device 0) ...............50
3.5.11 SVID—Subsystem Vendor Identification (Device 0) .............................51
3.5.12 SID—Subsystem Identification (Device 0) ............................................51
3.5.13 CAPPTR—Capabilities Pointer (Device 0) ............................................51
3.5.14 AGPM—AGP Miscellaneous Configuration Register (Device 0)...........52
3.5.15 DRB[0:7]—DRAM Row Boundary Registers (Device 0)........................52
3.5.16 DRA—DRAM Row Attribute Registers (Device 0) ................................53
3.5.17 DRT—DRAM Timing Register (Device 0) .............................................55
3.5.18 DRC—DRAM Controller Mode Register (Device 0) ..............................56
3.5.19 DERRSYN—DRAM Error Syndrome Register (Device 0) ....................58
3.5.20 EAP—Error Address Pointer Register (Device 0) .................................58
3.5.21 PAM[0:6]—Programmable Attribute Map Registers (Device 0) ...........59
3.5.22 FDHC—Fixed DRAM Hole Control Register (Device 0)........................62
3.5.23 SMRAM—System Management RAM Control Register (Device 0) ......63
3.5.24 ESMRAMC—Extended System Mgmt RAM Control
Register (Device 0)................................................................................64
3.5.25 ACAPID—AGP Capability Identifier Register (Device 0).......................65
3.5.26 AGPSTAT—AGP Status Register (Device 0) .......................................66
3.5.27 AGPCMD—AGP Command Register (Device 0)..................................67
3.5.28 AGPCTRL—AGP Control Register (Device 0)......................................68
3.5.29 APSIZE—Aperture Size (Device 0) .......................................................69
3.5.30 ATTBASE—Aperture Translation Table Base Register (Device 0).......70
3.5.31 AMTT—AGP Interface Multi-Transaction Timer Register (Device 0) ...71
3.5.32 LPTT—AGP Low Priority Transaction Timer Register (Device 0).........72
3.5.33 TOM—Top of Low Memory Register (Device 0) ...................................73
3.5.34 MCHCFG—MCH Configuration Register (Device 0).............................74
3.5.35 ERRSTS—Error Status Register (Device 0) .........................................75
3.5.36 ERRCMD—Error Command Register (Device 0) .................................76
3.5.37 SMICMD—SMI Command Register (Device 0) ....................................78
3.5.38 SCICMD—SCI Command Register (Device 0) .....................................78
3.5.39 SKPD—Scratchpad Data Register (Device 0) ......................................79
3.5.40 CAPID—Product Specific Capability Identifier Register (Device 0) ......79
3.6 Bridge Registers (Device 1) ..................................................................................80
3.6.1 VID1—Vendor Identification Register (Device 1) ..................................81
3.6.2 DID1—Device Identification Register (Device 1)...................................81
3.6.3 PCICMD1—PCI-PCI Command Register (Device 1)............................82
3.6.4 PCISTS1—PCI-PCI Status Register (Device 1)....................................83
3.6.5 RID1—Revision Identification Register (Device 1)................................84
3.6.6 SUBC1—Sub-Class Code Register (Device 1).....................................84
3.6.7 BCC1—Base Class Code Register (Device 1)......................................84
3.6.8 MLT1—Master Latency Timer Register (Device 1) ...............................85
3.6.9 HDR1—Header Type Register (Device 1) ............................................85
3.6.10 PBUSN1—Primary Bus Number Register (Device 1) ...........................85
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Intel^® 82845 MCH for SDR Datasheet