RG82845SL5YQ Datasheet, PDF (113/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Functional Description
R
Table 15. AGP Commands Supported by the Intel^® MCH When Acting as an AGP Target
AGP
Command
C/BE[3:0]#
Encoding
MCH Host Bridge
Cycle Destination
Response as PCIx Target
Read
Hi-Priority Read
Reserved
0000
0000
0001
0000
0010
System memory
Hub interface
System memory
The Hub interface
N/A
Low-priority read
Complete with random data
High-priority read
Complete with random data
No response
Reserved
Write
Hi-Priority Write
0011
0100
0100
0101
0101
N/A
System memory
Hub interface
System memory
Hub interface
Reserved
Reserved
Long Read
Hi-Priority Long
Read
Flush
Reserved
Fence
Reserved
Reserved
Reserved
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
N/A
N/A
System memory
Hub interface
System memory
Hub interface
MCH
N/A
MCH
N/A
N/A
N/A
No response
Low-priority write
Cycle goes to DRAM with byte
enables inactive
High-priority write
Cycle goes to DRAM with byte
enables inactive; does not go to
the hub interface
No response
No response
Low-priority read
Complete locally with random data;
does not go to the hub interface
High-priority read
Complete with random data
Complete with QW of random data
No response
No response; Flag inserted in
MCH request queue
No response
No response
No response
NOTES:
1. N/A refers to a function that is not applicable
As a target of an AGP cycle, the MCH supports all the transactions targeting system memory
(summarized in Table 15). The MCH supports both normal and high-priority read and write
requests. The MCH does not support AGP cycles to the hub interface. PIPE# and SBA cycles do
not require coherency management and all AGP initiator accesses to system memory, using AGP
PIPE# or SBA protocol, are treated as non-snoopable cycles. These accesses are directed to the
AGP aperture in system memory that is programmed as either uncacheable (UC) memory or write
combining (WC) in the processor’s MTRRs.
Intel^® 82845 MCH for SDR Datasheet
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