RG82845SL5YQ Datasheet, PDF (115/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Functional Description
R
Table 16. Data Rate Control Bits
AGPCNTL
.FWCE
0
1
1
1
AGPCMD.
FWPE
0
1
1
1
AGPCMD.
DRATE
[bit 2]
X
0
0
1
AGPCMD.
DRATE
[bit 1]
X
0
1
0
AGPCMD.
DRATE
[bit 0]
X
1
0
0
MCH =>AGP Master Write
Protocol
1x
1x
2x strobing
4x strobing
5.3.6 AGP FRAME# Transactions on AGP
The MCH accepts and generates AGP FRAME# transactions on the AGP bus. The MCH
guarantees that AGP FRAME# accesses to system memory are kept coherent with the processor
caches by generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not
supported.
MCH Initiator and Target Operations
Table 17 summarizes MCH target operation for AGP FRAME# initiators. The cycles can be either
destined to system memory or the hub interface.
Table 17. PCI Commands Supported by the Intel^® MCH (When Acting as a FRAME# Target)
PCI Command
C/BE[3:0]#
Intel^® MCH
Interrupt Acknowledge
Special cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Encoding
0000
0001
0010
0011
0100
0101
0110
0110
0111
0111
1000
1001
1010
1011
1100
1100
Cycle Destination
N/A
N/A
N/A
N/A
N/A
N/A
System memory
Hub interface
System memory
Hub interface
N/A
N/A
N/A
N/A
System memory
Hub interface
Response as a FRAME#
Target
No response
No response
No response
No response
No response
No response
Read
No response
Posts data
No response
No response
No response
No response
No response
Read
No response
Intel^® 82845 MCH for SDR Datasheet
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