RG82845SL5YQ Datasheet, PDF (118/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Functional Description
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5.4.2
5.5
5.6
Sleep State Control
• S0 (Awake): In this state all power planes are active. All of the ACPI software “C” states are
embedded in this state.
• S1: The recommended implementation of S1 state is the same as C2 state (Stop Grant), which
is entered by the assertion of the STPCLK# signal from the ICH2 to the processor. A further
power saving can be achieved by asserting processor SLP# from the ICH2. This puts the
processor into Sleep State.
• S2: ACPI S2 state is not supported in the 845 chipset desktop platform.
• S3 (Suspend To RAM (STR)): The next level of power reduction occurs when the clock
synthesizers and main power planes (ICH2, MCH, and the processor) are shut down but the
system memory plane and the ICH2 resume well remain active. This is the Suspend-to-RAM
(STR) state. All clocks from synthesizers are shut down during the S3 state.
• S4 and S5 (Suspend To Disk (STD), Soft Off): The next level of power reduction occurs
when the memory power and MCH are shut down in addition to the clock synthesizers, ICH2,
and the processor power planes. The ICH2 resume well is still powered.
• G3 (Mechanical Off): In this state only the RTC well is powered. The system can only
reactivate when the power switch is returned to the “On” position.
Intel^® MCH Clocking
The 845 chipset is supported by the CK_408 compliant clock synthesizer. For details on clocking,
refer to the Intel^® Pentium 4 Processor in a 478 Pin Package and Intel^® 845 Chipset Platform
Design Guide.
Intel^® MCH System Reset and Power Sequencing
For details on MCH system reset and power sequencing, refer to the Intel^® Pentium 4 Processor in
a 478 Pin Package and Intel^® 845 Chipset Platform Design Guide.
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Intel^® 82845 MCH for SDR Datasheet