RG82845SL5YQ Datasheet, PDF (80/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.6
Bridge Registers (Device 1)
Table 10. provides the register address map for Device 0 PCI configuration space. An “s” in the
Default Value column indicates that a strap determines the power-up default value for that bit.
Table 10. Intel^® MCH Configuration Space (Device 1)
Address
Offset
00-01h
02–03h
04–05h
06–07h
08
09
0Ah
0Bh
0Ch
0Dh
0Eh
0F–17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
22–23h
24–25h
26–27h
28–3Dh
3Eh
3Fh
40h
41–4Fh
50–57h
Symbol
VID1
DID1
PCICMD1
PCISTS1
RID1
—
SUBC1
BCC1
—
MLT1
HDR1
—
PBUSN1
SBUSN1
SUBUSN1
SMLT1
IOBASE1
IOLIMIT1
SSTS1
MBASE1
MLIMIT1
PMBASE1
PMLIMIT1
—
BCTRL1
—
ERRCMD1
—
DWTC
Name
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Reserved
Sub-Class Code
Base Class Code
Reserved
Master Latency Timer
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Bus Master Latency Timer
I/O Base Address
I/O Limit Address
Secondary Status
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Reserved
Bridge Control
Reserved
Error Command
Reserved
DRAM Write Thermal Management Control
Default
Access
8086h
1A31h
0000h
00A0h
03h, 04h
—
04h
06h
—
00h
01h
—
00h
00h
00h
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
—
00h
—
00h
—
0000000
0h
RO
RO
RO, R/W
RO, R/WC
RO
—
RO
RO
—
R/W
RO
—
RO
R/W
R/W
R/W
R/W
R/W
RO, R/WC
R/W
R/W
R/W
R/W
—
RO, R/W
—
R/W
—
R/W/L
80
Intel^® 82845 MCH for SDR Datasheet