RG82845SL5YQ Datasheet, PDF (43/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.5
Host-Hub Interface Bridge Device Registers
(Device 0)
Table 8 provides the register address map for Device 0 PCI configuration space. An “s” in the
Default Value column indicates that a strap determines the power-up default value for that bit.
Table 8. Intel^® MCH Configuration Space (Device 0)
Address
Offset
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Dh
0Eh
0Fh
10–13h
14–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
35–50h
51h
52–5Fh
60–67h
68–6Fh
70–73h
73–77h
78–7Bh
7C–7Fh
80–85h
86h
Register
Symbol
Register Name
VID
DID
PCICMD
PCISTS
RID
—
SUBC
BCC
MLT
HDR
—
APBASE
—
SVID
SID
—
CAPPTR
—
AGPM
—
DRB[0:7]
—
DRA
—
DRT
DRC
—
DERRSYN
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Reserved.
Sub-Class Code
Base Class Code
Master Latency Timer
Header Type
Reserved.
Aperture Base Configuration
Reserved.
Subsystem Vendor Identification
Subsystem Identification
Reserved.
Capabilities Pointer
Reserved.
AGP Miscellaneous Configuration
Reserved.
DRAM Row Boundary (8 registers)
Reserved.
DRAM Row Attribute (4 registers)
Reserved.
DRAM Timing Register
DRAM Controller Mode
Reserved.
DRAM Error Syndrome
Default
Value
8086h
1A30h
0006h
0090h
03h, 04h
—
00h
06h
00h
00h
—
00000008h
—
0000h
0000h
—
A0h
—
00h
—
00h
—
00h
—
00000010h
0000h
—
00h
Access
RO
RO
RO, R/W
RO, R/WC
RO
—
RO
RO
RO
RO
—
RO, R/W
—
R/WO
R/WO
—
RO
—
R/W
—
R/W
—
R/W
—
R/W
R/W, RO
—
RO
Intel^® 82845 MCH for SDR Datasheet
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