RG82845SL5YQ Datasheet, PDF (17/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Introduction
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1.4.5 Hub Interface
The 8-bit hub interface connects the MCH to the ICH2. All communication between the MCH and
the ICH2 occurs over the hub interface. The hub interface runs at 66 MHz / 266 MB/s. In addition
to the normal traffic types, the following communication also occurs over the hub interface:
• Interrupt related messages
• Power management events as messages
• SMI, SCI, and SERR error indication messages
It is assumed that the hub interface is always connected to an ICH2.
1.4.6 Intel^® MCH Clocking
The MCH has the following clock input pins:
• Differential BCLK for the host interface
• 66 MHz clock input for the AGP and hub interface
Clock synthesizer chip(s) generate the system host clocks, AGP and hub interface clocks, and PCI
clocks. The system bus target speed is 400 MHz. The MCH does not require any relationship
between the HCLKIN host clock and the 66 MHz clock generated for AGP and the hub interface;
they are asynchronous to each other. The AGP and hub interface runs at a constant 66 MHz base
frequency. The hub interface runs at 4x. AGP transfers can be 1x, 2x, or 4x. Table 5 indicates the
supported frequency ratios between the various interfaces.
Table 5. Intel^® MCH Clock Ratio Table
Interface
Memory
AGP
Hub interface
Speed
SDR 133 MHz
66 MHz
66 MHz
Processor BCLK
(100 MHz)
3:4 synchronous
Asynchronous
Asynchronous
Intel^® 82845 MCH for SDR Datasheet
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