RG82845SL5YQ Datasheet, PDF (37/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.4.1
DRAMWIDTH—DRAM Width Register
Address Offset:
Default Value:
Access:
Size:
2Ch
00h
R/W
8 bits
This register determines the width of SDRAM devices populated in each row of memory.
Bit
Descriptions
7:6
Reserved.
5
Row 5 Width. Width of devices in Row 5
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
4
Row 4 Width. Width of devices in Row 4
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
3
Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
2
Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
1
Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
0
Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify
exactly which row width field affects which clock signal.
Row Parameters
0
1
2
3
4
5
SDR Clocks Affected
SCK[0], SCK[2]
SCK[1], SCK[3]
SCK[4], SCK[6]
SCK[5], SCK[7]
SCK[8], SCK[10]
SCK[9], SCK[11]
Intel^® 82845 MCH for SDR Datasheet
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