RG82845SL5YQ Datasheet, PDF (71/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.5.31
AMTT—AGP Interface Multi-Transaction Timer Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
BCh
00h
R/W
8 bits
AMTT is an 8-bit register that controls the amount of time that the MCH arbiter allows AGP
master to perform multiple back-to-back transactions. The MCH AMTT mechanism is used to
optimize the performance of the AGP master (using PCI protocol) that performs multiple back-to-
back transactions to fragmented memory ranges (and as a consequence it can not use long burst
transfers). The AMTT mechanism applies to the host-AGP transactions as well and it guarantees
to the processor a fair share of the AGP interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current agent (either AGP master or host bridge) after which the
AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables
this function. The AMTT value can be programmed with 8-clock granularity. For example, if the
AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP
(66 MHz) clocks.
Bit
Description
7:3
Multi-Transaction Timer Count Value (MTTC). The number programmed in these bits
represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to
the current agent (either AGP master or MCH) after which the AGP arbiter will grant the bus to
another agent.
2:0
Reserved.
Intel^® 82845 MCH for SDR Datasheet
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