RG82845SL5YQ Datasheet, PDF (84/148 Pages) Intel Corporation – Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR

Register Description
R
3.6.5
3.6.6
3.6.7
RID1—Revision Identification Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
08h
See RID1 table below
RO
8 bits
This register contains the revision number of the MCH device 1. These bits are read only and
writes to this register have no effect.
Bit
Description
7:0
Revision Identification Number (RID): This is an 8-bit value that indicates the revision
identification number for the MCH device 1.
03h = A3 Stepping
04h = B0 Stepping
SUBC1—Sub-Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Ah
04h
RO
8 bits
This register contains the Sub-Class Code for the MCH device 1.
Bit
Description
7:0
Sub-Class Code (SUBC1): This is an 8-bit value that indicates the category of bridge of the
MCH.
04h = Host bridge.
BCC1—Base Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
RO
8 bits
This register contains the Base Class Code of the MCH device 1.
Bit
Description
7:0
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the
MCH device 1.
06h = Bridge device.
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Intel^® 82845 MCH for SDR Datasheet