HD64F3670 Datasheet, PDF (91/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name Initial Value
7 SMSEL 0
6−
0
5 DTON
0
4 MA2
0
3 MA1
0
2 MA0
0
1−
0
0−
0
Legend X: Don't care.
R/W Description
R/W Sleep Mode Selection
This bit selects the mode to transit after the execution of a
SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6-2.
−
Reserved
This bit is always read as 0, and cannot be modieied
R/W Direct Transfer on Flag
This bit selects the mode to transit after the execution of a
SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6-2.
R/W Active Mode Clock Select 2 to 0
R/W These bits select the operating clock frequency in the
R/W ^{active and sleep modes. The operating clock frequency}
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φ_OSC
100: φ_OSC/8
101: φ_OSC/16
110: φ_OSC/32
111: φ_OSC/64
−
Reserved
−
These bits are always read as 0, and cannot be modified.
6.1.3 Module Standby Control Register 1(MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Rev. 1.0, 03/01, page 67 of 280