HD64F3670 Datasheet, PDF (182/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name
1 CKS1
0 CKS0
Initial Value R/W
0
R/W
0
R/W
Description
Clock Select 0 and 1
These bits select the clock source for the baud
rate generator.
00: ø clock (n = 0)
01: ø/4 clock (n = 1)
10: ø/16 clock (n = 2)
11: ø/64 clock (n = 3)
For the relationship between the bit rate register
setting and the baud rate, see section 13.3.8, Bit
Rate Register (BRR). n is the decimal
representation of the value of n in BRR (see
section 13.3.8, Bit Rate Register (BRR)).
13.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to selection of the transfer clock source. For details on interrupt requests, refer to section
13.7, Interrupts.
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request
is enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit s set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Rev. 1.0, 03/01, page 158 of 280