HD64F3670 Datasheet, PDF (198/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 13-5 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 13-8 shows a sample flow chart
for serial data reception.
No
Yes
(A)
Start reception
[1]
Read OER, PER, and
FER flags in SSR
[1]
[2]
OER+PER+FER = 1
Yes
[4]
No
Error processing ^[3]
(Continued on next page)
Read RDRF flag in SSR
[2]
[4]
RDRF = 1
Yes
Read receive data in RDR
All data received?
[3]
Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. The RDRF
flag is cleared automatically.
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
The RDRF flag is cleared automatically.
If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
No
Clear RE bit in SCR3 to 0
<End>
Figure 13-8 Sample Serial Reception Data Flowchart (Asynchronous mode)(1)
Rev. 1.0, 03/01, page 174 of 280