HD64F3670 Datasheet, PDF (225/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 14-3 A/D Conversion Time (Single Mode)
Item
Symbol
Min
A/D conversion start delay t_D
6
Input sampling time
t_SPL
—
A/D conversion time
t_CONV
131
Note: All values represent the number of states.
CKS = 0
Typ Max
—
9
31
—
CKS = 1
Min Typ Max
4
—
5
—
15
—
14.4.4 External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 14-3
shows the timing.
ø
Internal trigger signal
ADST
A/D conversion
Figure 14-3 External Trigger Input Timing
Rev. 1.0, 03/01, page 201 of 280