HD64F3670 Datasheet, PDF (66/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 3-1 Exception Sources and Vector Address
Exception Sources
Reset
Reserved for system use
NMI
Trap instruction (#0)
(#1)
(#2)
(#3)
Break conditions satisfied
Direct transition by executing the SLEEP instruction
IRQ0
IRQ3
WKP
Reserved for system use
Timer W
Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
Timer V
Timer V compare match A
Timer V compare match B
Timer V overflow
SCI3
SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
A/D conversion end
Vector
Number
0
1 to 6
7
8
9
10
11
12
13
14
17
18
20
21
22
23
25
Vector Address
H'0000 to H'0001
H'0002 to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D
H'0022 to H'0023
H'0024 to H'0025
H'0028 to H'0029
H'002A to H'002B
H'002C to H'002D
H'002E to H'002F
H'0032 to H'0033
Rev. 1.0, 03/01, page 42 of 280