HD64F3670 Datasheet, PDF (143/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

10.5 Timer V application examples
10.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 10-9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
H'FF
TCORA
TCNTV
Counter cleared
TCORB
H'00
TMOV
Figure 10-9 Pulse Output Example
Rev. 1.0, 03/01, page 119 of 280