HD64F3670 Datasheet, PDF (100/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

7.2.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit Bit Name
7
FLER
6
—
5
—
4
—
3
—
2
—
1
—
0
—
Initial Value R/W
0
R
0
—
0
—
0
—
0
—
0
—
0
—
0
—
Description
Flash Memory Error
Indicates that an error has occurred during an
operation on flash memory (programming or erasing).
When FLER is set to 1, flash memory goes to the
error-protection state.
See 7.5.3, Error Protection, for details.
Reserved
These bits are always read as 0 and cannot be
modified.
7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit Bit Name
7
—
6
—
5
—
4
EB4
3
EB3
2
EB2
1
EB1
0
EB0
Initial Value
0
0
0
R/W
—
—
—
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
When this bit is set to 1, 16 kbytes of H'1000 to
H'4FFF will be erased.
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF
will be erased.
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF
will be erased.
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF
will be erased.
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF
will be erased.
Rev. 1.0, 03/01, page 76 of 280