HD64F3670 Datasheet, PDF (186/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13-2
shows the relationship between the N setting in BRR and the N setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 13-3 shows the maximum bit rate for each frequency in
asynchronous mode. The value shown in both tables 13-2 and 13-3 are values in active (high-
speed) mode. Table 13-4 shows the relationship between the N setting in BRR and the N setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 13-4 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous mode]
φ × (10⁶ – 1)
N=
64 × 2^2n–1 × B

φ × 10⁶
Error(%) = 

B ×64 × 2^2n–1 × (N + 1)
-1
× 100
[Clocked synchronous mode]
φ × (10⁶ – 1)
N=
8 × 2^2n–1 × B
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: SMR
Rev. 1.0, 03/01, page 162 of 280