HD64F3670 Datasheet, PDF (151/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name Initial Value R/W
7 CTS
0
R/W
6−
1
−
5 BUFEB 0
R/W
4 BUFEA 0
R/W
3−
1
−
2 PWMD 0
R/W
1 PWMC 0
R/W
0 PWMB 0
R/W
Description
Counter Start
The counter operation is halted when this bit is 0; while it
can be performed when this bit is 1.
Reserved
This bit is always read as 1 and cannot be modified.
Buffer Operation B
Selects the GRD function.
0: GRD operates as an input capture/output compare
register
1: GRD operates as the buffer register for GRB
Buffer Operation A
Selects the GRC function.
0: GRC operates as an input capture/output compare
register
1: GRC operates as the buffer register for GRA
Reserved
This bit is always read as 1 and cannot be modified.
PWM Mode D
Selects the output mode of the FTIOD pin.
0: FTIOD operates normally (output compare output)
1: PWM output
PWM Mode C
Selects the output mode of the FTIOC pin.
0: FTIOC operates normally(output compare output)
1: PWM output
PWM Mode B
Selects the output mode of the FTIOB pin.
0: FTIOB operates normally(output compare output)
1: PWM output
Rev. 1.0, 03/01, page 127 of 280