HD64F3670 Datasheet, PDF (11/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

11.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................146
11.6 Usage Notes ......................................................................................................................147
Section 12 Watchdog Timer ............................................................................. 149
12.1 Features .............................................................................................................................149
12.2 Register Descriptions ........................................................................................................149
12.2.1 Timer Control/Status Register WD(TCSRWD)...................................................150
12.2.2 Timer Counter WD(TCWD) ................................................................................151
12.2.3 Timer Mode Register WD(TMWD) ....................................................................151
12.3 Operation...........................................................................................................................152
Section 13 Serial Communication Interface3 (SCI3) ....................................... 153
13.1 Features .............................................................................................................................153
13.2 Input/Output Pins ..............................................................................................................155
13.3 Register Descriptions ........................................................................................................155
13.3.1 Receive Shift Register (RSR)...............................................................................156
13.3.2 Receive Data Register (RDR) ..............................................................................156
13.3.3 Transmit Shift Register (TSR) .............................................................................156
13.3.4 Transmit Data Register (TDR).............................................................................156
13.3.5 Serial Mode Register (SMR)................................................................................157
13.3.6 Serial Control Register 3 (SCR3).........................................................................158
13.3.7 Serial Status Register (SSR).................................................................................160
13.3.8 Bit Rate Register (BRR) ......................................................................................162
13.4 Operation in Asynchronous Mode ....................................................................................167
13.4.1 Clock.................................................................................................................... 168
13.4.2 SCI3 Initialization ................................................................................................169
13.4.3 Data Transmission ...............................................................................................170
13.4.4 Serial Data Reception...........................................................................................172
13.5 Operation in Clocked Synchronous Mode ........................................................................176
13.5.1 Clock.................................................................................................................... 176
13.5.2 SCI3 Initialization ................................................................................................176
13.5.3 Serial Data Transmission .....................................................................................177
13.5.4 Serial Data Reception (Clocked Synchronous Mode)..........................................179
13.5.5 Simultaneous Serial Data Transmission and Reception.......................................181
13.6 Multiprocessor Communication Function.........................................................................183
13.6.1 Multiprocessor Serial Data Transmission ............................................................185
13.6.2 Multiprocessor Serial Data Reception .................................................................186
13.7 Interrupts ...........................................................................................................................190
13.8 Usage Notes ......................................................................................................................191
13.8.1 Break Detection and Processing ..........................................................................191
13.8.2 Mark State and Break Detection ..........................................................................191
13.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
191
Rev. 2.0, 03/01, Page xi of xxiv