HD64F3670 Datasheet, PDF (166/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

11.5 Operation Timing
11.5.1 TCNT Count Timing
Figure 11-14 shows the TCNT count timing when the internal clock source is selected. Figure 11-
15 shows the timing when the external clock source is selected. The pulse width of the external
clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted
correctly.
φ
Internal
clock
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 11-14 Count Timing for Internal Clock Source
φ
External
clock
TCNT input
clock
TCNT
Rising edge
N
Rising edge
N+1
N+2
Figure 11-15 Count Timing for External Clock Source
11.5.2 Output Compare Timing
The compare match signal is generated in the last state in which TCNT and the general register
match (when TCNT changes from the matching value to the next value). When the compare match
signal is generated, the output value selected in TIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches a general register, the compare match
signal is generated only after the next counter clock pulse is input.
Rev. 1.0, 03/01, page 142 of 280