HD64F3670 Datasheet, PDF (191/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.4 Operation in Asynchronous Mode
Figure 13-2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units,
enabling full-duplex. Both the transmitter and the receiver also have a double-buffered structure,
so data can be read or written during transmission or reception, enabling continuous data transfer.
1
LSB
MSB
Serial _{0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1}
1
data
Start
bit
Transmit/receive data
Parity Stop bit
bit
1 bit
7 or 8 bits
1 bit,
1 or
or none 2 bits
Idle state
(mark state)
1
One unit of transfer data (character or frame)
Figure 13-2 Data Format in Asynchronous Communication
Rev. 1.0, 03/01, page 167 of 280