HD64F3670 Datasheet, PDF (7/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Contents
Section 1 Overview....................................................................................................................1
1.1 Overview...........................................................................................................................1
1.2 Internal Block Diagram.....................................................................................................2
1.3 Pin Arrangement ...............................................................................................................3
1.4 Pin Functions ....................................................................................................................5
Section 2 CPU................................................................................................... 7
2.1 Address Space and Memory Map .....................................................................................8
2.2 Register Configuration ...................................................................................................... 9
2.2.1 General Registers .....................................................................................................10
2.2.2 Program Counter (PC) .............................................................................................11
2.2.3 Condition-Code Register (CCR) .............................................................................. 11
2.3 Data Formats .....................................................................................................................13
2.3.1 General Register Data Formats ................................................................................13
2.3.2 Memory Data Formats .............................................................................................15
2.4 Instruction Set ...................................................................................................................16
2.4.1 Table of Instructions Classified by Function ...........................................................16
2.4.2 Basic Instruction Formats ........................................................................................25
2.5 Addressing Modes and Effective Address Calculation .....................................................27
2.5.1 Addressing Modes ...................................................................................................27
2.5.2 Effective Address Calculation .................................................................................29
2.6 Basic Bus Cycle ................................................................................................................32
2.6.1 Access to On-Chip Memory (RAM, ROM).............................................................32
2.6.2 On-Chip Peripheral Modules ...................................................................................33
2.7 CPU States ........................................................................................................................34
2.8 Usage Notes ......................................................................................................................35
2.8.1 Notes on Data Access to Empty Areas ....................................................................35
2.8.2 EEPMOV Instruction...............................................................................................35
2.8.3 Bit Manipulation Instruction....................................................................................35
Section 3 Exception Handling .......................................................................... 41
3.1 Exception Sources and Vector Address ............................................................................41
3.2 Register Descriptions ........................................................................................................43
3.2.1 Interrupt Edge Select Register 1(IEGR1) ................................................................43
3.2.2 Interrupt Edge Select Register 2(IEGR2) ................................................................44
3.2.3 Interrupt Enable Register 1(IENR1) ........................................................................45
3.2.4 Interrupt Flag Register 1(IRR1) ...............................................................................46
3.2.5 Wakeup Interrupt Flag Register(IWPR) ..................................................................47
3.3 Reset .................................................................................................................................48
3.4 Interrupt Exception Handling............................................................................................48
Rev. 2.0, 03/01, Page vii of xxiv