HD64F3670 Datasheet, PDF (90/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name Initial Value
7 SSBY
0
6 STS2
0
5 STS1
0
4 STS0
0
3to0 −
0
R/W Description
R/W Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: a transition is made to the sleep mode
1: a transition is made to the standby mode.
For details, see table 6-2.
R/W Standby Timer Select 2 to 0
R/W These bits designate the time the CPU and peripheral
R/W ^{modules wait for stable clock operation after exiting from}
the standby mode, to the active mode or sleep mode due
to an interrupt. The designation should be made according
to the clock frequency so that the waiting time is at least
10 ms. The relationship between the specified value and
the number of wait states is shown in table 6-1. When an
external clock is to be used, the minimum value (STS2 =
STS1 = STS0 =1) is recommended.
−
Reserved
These bits are always read as 0 and cannot be modified.
Table 6-1 Operating Frequency and Waiting Time
STS2 STS1 STS0 Waiting Time
0
0
0
8,192 states
1
16,384 states
1
0
32,768 states
1
65,536 states
1
0
0
131,072 states
1
1,024 states
1
0
128 states
1
16 states
Note: Time unit is ms
16 MHz 10 MHz 8 MHz
0.5
0.8
1.0
1.0
1.6
2.0
2.0
3.3
4.1
4.1
6.6
8.2
8.2
13.1 16.4
0.06 0.10 0.13
0.00 0.01 0.02
0.00 0.00 0.00
4 MHz
2.0
4.1
8.2
16.4
32.8
0.26
0.03
0.00
2 MHz
4.1
8.2
16.4
32.8
65.5
0.51
0.06
0.01
1 MHz 0.5 MHz
8.1
16.4
16.4 32.8
32.8 65.5
65.5 131.1
131.1 262.1
1.02 2.05
0.13 0.26
0.02 0.03
6.1.2 System Control Register 2(SYSCR2)
The SYSCR2 register controls the power-down modes, as well as SYSCR1.
Rev. 1.0, 03/01, page 66 of 280