HD64F3670 Datasheet, PDF (167/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Figure 11-16 shows the output compare timing.
φ
TCNT input
clock
TCNT
N
N+1
GRA to GRD
N
Compare
match signal
FTIOA to FTIOD
Figure 11-16 Output Compare Output Timing
11.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 11-17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
ø
Input capture
input
Input capture
signal
TCNT
N–1
N
N+1
N+2
GRA to GRD
N
Figure 11-17 Input Capture Input Signal Timing
Rev. 1.0, 03/01, page 143 of 280