HD64F3670 Datasheet, PDF (244/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Item
Test
Symbol Condition
Values
Min Typ Max Unit
Erase
Wait time after SWE
x
bit setting*¹
1
—
—
µs
Wait time after ESU
y
bit setting*¹
100 —
—
µs
Wait time after E bit
z
setting*¹*⁶
Wait time after E bit clear*¹ α
Wait time after ESU bit clear*¹ β
10
—
100 ms
10
—
—
µs
10
—
—
µs
Wait time after EV
γ
bit setting*¹
Wait time after dummy write*¹ ε
Wait time after EV bit clear*¹ η
20
—
—
µs
2
—
—
µs
4
—
—
µs
Wait time after SWE
θ
bit clear*¹
Maximum erase count*¹*⁶*⁷ N
100 —
—
—
—
µs
120 Times
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash
memory control register 1 (FLMCR1) is set. The program-verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (t_P(MAX)) = wait time after P bit setting (z) ×
maximum number of writes (N)
5. Set the maximum number of writes (N) according to the actual set values of z1, z2, and
z3, so that it does not exceed the programming time maximum value (t (MAX)). The
P
wait time after P bit setting (z1, z2) should be changed as follows according to the value
of the number of writes (n).
Number of writes (n)
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (t_E(max)) = wait time after E bit setting (z) × maximum
number of erases (N)
7. Set the maximum number of erases (N) according to the actual set value of (z), so that
it does not exceed the erase time maximum value (t_E(max)).
Rev. 1.0, 03/01, page 220 of 280