HD64F3670 Datasheet, PDF (67/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.2 Register Descriptions
Interrupts are controlled by the following registers. For details on register addresses and register
states during each processing, refer to appendix B, Internal I/O Register.
• Interrupt Edge Select Register 1(IEGR1)
• Interrupt Edge Select Register 2(IEGR2)
• Interrupt Enable Register 1(IENR1)
• Interrupt Flag Register 1(IRR1)
• Wakeup Interrupt Flag Register(IWPR)
3.2.1 Interrupt Edge Select Register 1(IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and
IRQ0.
Bit Bit Name Initial Value R/W
7−
0
−
6−
1
−
5−
1
−
4−
1
−
3 IEG3
0
R/W
2−
0
−
1−
0
−
0 IEG0
0
R/W
Description
Reserved
This bit is always read as 0, and cannot be modified.
Reserved
These bits are always read as 1, and cannot be modified.
IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
Reserved
This bit is always read as 0, and cannot be modified.
Reserved
This bit is always read as 0, and cannot be modified.
IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
Rev. 1.0, 03/01, page 43 of 280