HD64F3670 Datasheet, PDF (106/305 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time=programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
START
Set SWE bit in FLMCR1
Wait 1 µs
Store 128-byte program data in program
data area and reprogram data area
n= 1
m= 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Apply Write pulse
Set PV bit in FLMCR1
Wait 4 µs
Set block start address as
verify address
Increment address
H'FF dummy write to verify address
Wait 2 µs
Read verify data
Verify data =
No
write data?
Yes
No
n≤6?
Yes
Additional-programming data computation
m=1
Reprogram data computation
n←n+1
128-byte
No
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
No
n ≤ 6?
Yes
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m= 0 ?
No
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
Yes
n ≤ 1000 ?
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure
Figure 7-3 Program/Program-Verify Flowchart
Table 7-4 Reprogram Data Computation Table
Program Data
0
0
1
1
Verify Data
0
1
0
1
Reprogram Data
1
0
1
1
Comments
Programming completed
Reprogram bit
—
Remains in erased state
Rev. 1.0, 03/01, page 82 of 280